1. Field
The disclosure relates to semiconductor based image sensors and more particularly to backside illuminated Active Pixel image Sensors (APS) with advanced pixel level signal processing capabilities using capacitively coupled readout integrated circuits (ROICs).
2. Related Art
Conventional APS are defined by solid state imaging devices having an array of pixels arranged in columns and rows. Each pixel contains both a photo sensing means and at least one other active component which create a charge that is converted to a voltage or a current signal. The converted signal indicates the amount of light incident upon a pixel. Conventional image sensors were limited to silicon charge coupled devices (CCDs). Over the years, CCDs have become the standard for visible image sensors. The fabrication process for silicon CCDs has always been expensive and complex. As a result, considerable attention has been paid to developing complementary metal-oxide (CMOS) technology as a replacement for the silicon CCDs. As of late, CMOS technology has become the technology of choice, utilized by most foundries for making image sensors, due to its capability of integrating advanced signal processing capabilities with image sensors monolithically on the same die, thus reducing the overall imaging system cost and simplifying system design.
Conventional CMOS technology advantageously places the Readout Integrated Circuit (ROIC) at or near the pixel. Conventional CMOS active pixel sensors rely on each pixel having a charge to voltage conversion amplifier to create local voltages representative of the illumination level recorded at the pixel. FIG. 1 shows a circuit schematic of a prior art CMOS APS pixel.
Referring to FIG. 1, detector 100 receives incident rays 110 at photodetector diode 120. Photon energy is absorbed by detector 100 and generated electrons are captured by the depletion capacitance of the reverse biased photodetector diode 120. These photo-generated electrons alter the pre-defined node voltage 125 across the diode capacitance proportional to the absorbed photons by the pixel, and hence alter the recorded intensity level of the scene being imaged. The pre-defined pixel voltage is established by resetting the pixel depletion capacitance to a known reset voltage level 130 through the pixel reset transistor 140 using reset signal 145. Diode voltage is then buffered by a pixel buffer circuitry, in this case a source follower transistor 150, and connected to the monolithic readout circuits outside the imaging area through pixel select transistor 160 controlled by select signal 165 and a common signal bus 170 shared by all the pixels in a given column.
In some applications, a need exists for more signal processing capabilities other than just charge-to-voltage conversion and buffering. One such case is a high dynamic range imaging application, where the goal is to capture both very dim and bright objects in the same scene. For dim objects, a long exposure time is required to collect sufficiently large number of photons. On the contrary, a short exposure time is required for the very bright objects to avoid saturation and blooming in the pixel. One method to achieve high dynamic range is to use dual or multiple exposures, starting with a short exposure time and ending with a long exposure time. All pixel values need to be readout multiple times for all exposures, decreasing the maximum possible frame time. There is also a limit on the maximum exposure time due to the inherent dark current of the pixel. Therefore, a need exists for a more advanced techniques if one requires high dynamic range and reasonably high frame rates.
Another method to increase the dynamic range is to use pixel level circuitry that can achieve increased dynamic range in a single exposure between pixels of a given image frame. This method uses pixel level automatic or adaptive methods or numerical methods to increase the dynamic range independently for all pixels, which requires complicated pixels with increased transistor count. However, increased circuit complexity requires larger pixels to fit all the required analog and digital circuit blocks, reducing pixel count for a given chip size.
The circuitry disclosed in this document uses numerical methods to extend the dynamic range of the pixel independently; hence, it is possible to capture both very dim and bright pixels in a single exposure or frame. The circuitry uses common building elements used in previously reported high dynamic range pixel circuits. These common building blocks are listed as follows: integrator to accumulate generated charge captured by detectors, a sample and hold circuit to hold the integrator value, a reset circuit that resets the integrator when it reaches a built-in threshold value to avoid saturation and signal loss, a comparator that checks whether the integrator has reached the built-in threshold or not, a memory element that stores how many times the integrator is reset, and a high resolution analog-to-digital converter that reads out the sampled analog integrator output. There are four different methods to extend the dynamic range, and these are to use time-to-saturation, multiple-capture, synchronous self-reset with residue readout, and asynchronous self-reset with multiple capture. The method disclosed here is different than these, and can be considered as asynchronous self-reset with residue readout. It is asynchronous because the reset operation is not determined by a clocked comparator, but instead by a continuously operated comparator. It utilizes a residue readout method by digitizing the sampled analog integrator output. The advantage of asynchronous self-reset is that the integrator output varies the same amount between reset operations, hence it is possible to construct the extended dynamic range signal just using the integrator swing and the number of reset operations as well as the last value of the sampled integrator output. Therefore, it is not required to perform multiple sampling operations, and thus no fine pixel level analog-to-digital converter is needed. Residue digitization can be performed outside the pixel area either using on-chip video rate analog-to-digital converters serving large number of pixel columns or relatively low speed column-parallel analog-to-digital converters. Required memory for the reset count operations is implemented at the pixel level. Wide dynamic range information is generated by combining the count value of the reset operations, which acts as a Most Significant Bit (MSB) digitizer, and a fine residue value, which acts as a Least Significant Bit (LSB) digitizer.
With the help of 3-D circuit integration technology, it is also possible to distribute the pixel level signal processing into different physical layers vertically integrated as shown in FIG. 2. These physical layers 200 are implemented on different chips 210 and 220 connected at pixel level 230 and 240 using routing metals 270, through silicon vias 280, and indium bumps 290. A typical approach would be to perform electro-optical and analog functions in the first layer, which can be fabricated in a CMOS image sensor process with the emphasis on image sensor and analog performance, and digital functions can be integrated in the second layer, which can be fabricated in a fully digital CMOS process with very high device density. If required, additional layers can be added to the vertical stack of the chips 210 and 220.
However, a 3-D or vertical integration method involves a difficult and expensive fabrication process due to low yield of high-density through silicon via and indium bump based chip-to-chip interconnection processes. Therefore, a need exists for a simple and low-cost fabrication process to connect chips at pixel level to be able to distribute complex pixel functions into multiple layers.
Chip-to-chip signal transmission can also be done using a capacitive coupling technique, which does not require any through silicon via or indium bumps; therefore fabrication costs can be lowered considerably. It was first introduced as a method to provide an improved connectivity between chips to achieve low power and high data rates due to reduced parasitic, and implemented at pad level with a pitch of 50 μm without a need for high density connections. This work is focused on to provide a reliable means of alignment between memory and processor chips, and did not consider high interconnect density applications such as 3-D memories or image sensors where each element of a 2-D matrix requires a connection.
Later it has been demonstrated that it is possible to reduce the pitch and area required by the electrodes of the capacitive coupling circuits used for chip-to-chip interconnects. For example, reduced pitch values as small as 8 μm has been reported.